BARD_Verilog FIFO

구글, 챗GPT 대항마 AI 챗봇 ‘바드(Bard)’ 출시...'바드' 사용법은? - BTCC

구글, 챗GPT 대항마 AI 챗봇 ‘바드(Bard)’ 출시...'바드' 사용법은? - BTCC

Verilog

here is the Verilog code for a FIFO structure with 256 width and 64 depth:

module fifo (

  input clk,

  input reset,

  input [255:0] din,

  output reg [255:0] dout,

  output reg full,

  output reg empty,

  input wr,

  input rd

);

 

  reg [255:0] mem [63:0];

  integer i;

 

  always @(posedge clk or posedge reset) begin

    if (reset) begin

      for (i = 0; i < 64; i = i + 1) begin

        mem[i] <= 0;

      end

      full <= 0;

      empty <= 1;

    end else begin

      if (wr && !full) begin

        mem[head] <= din;

        head <= head + 1;

        if (head == 64) begin

          head <= 0;

        end

        if (!empty) begin

          empty <= 0;

        end

      end else if (rd && !empty) begin

        dout <= mem[tail];

        tail <= tail + 1;

        if (tail == 64) begin

          tail <= 0;

        end

        if (!full) begin

          full <= 1;

        end

      end

    end

  end

 

endmodule

 

Here is the test bench for the FIFO:

Verilog

module fifo_tb;

 

  reg clk, reset;

  reg wr, rd;

  wire [255:0] din, dout;

  wire full, empty;

 

  fifo fifo (

    .clk(clk),

    .reset(reset),

    .din(din),

    .dout(dout),

    .full(full),

    .empty(empty),

    .wr(wr),

    .rd(rd)

  );

 

  initial begin

    clk <= 0;

    forever #5 clk <= ~clk;

  end

 

  initial begin

    reset <= 1;

    #10 reset <= 0;

  end

 

  always @(posedge clk) begin

    din <= $random;

    wr <= $random;

    rd <= $random;

  end

 

endmodule

 

This code will create a FIFO with 256 width and 64 depth. The test bench will randomly generate data to be written to the FIFO and then read from the FIFO. The test bench will also check to make sure that the FIFO is not full and not empty.

The if logic in the always @(posedge clk or posedge reset) block checks the reset signal to determine whether the FIFO should be reset. If the reset signal is high, then the FIFO is reset and all of the data in the FIFO is cleared. If the reset signal is low, then the FIFO is not reset and the always @(posedge clk or posedge reset) block will continue to operate normally.

I hope this helps! Let me know if you have any other questions.

=============================

FEEDBACK:

posedge 문이 처음 리셋시그널 뜰때, full, empty 가 신호가 할당되는데 이 할당된 신호가 조건으로 다시 들어가는 구문이므로 동작이 잘 안될 수 있다.

최대한 posedge 문을 많이 만들어야 함.

한개의 posedge 구문에서 들어간 시그널은 그 구문에서의 if 조건안의 sensitivity list가 되면 안됨.

mem[head] 와 mem[tail] 로 나눈 것은 잘 했음.

짝수, 홀수 인덱스로 나눠서 Bandwidth를 늘리는 시도도 있을 것. (원하는 스펙은 따로 prompt 에 넣어 주어야 함)

--> prompt 조건 후 생성 코드 

# verilog code

module fifo (
  input clk,
  input reset,
  input [255:0] din,
  output reg [255:0] dout,
  output reg full,
  output reg empty,
  input wr,
  input rd
);

  reg [255:0] mem [63:0];
  reg [1:0] head, tail;
  reg [1:0] rd_idx, wr_idx;

  always @(posedge clk) begin
    if (reset) begin
      for (i = 0; i < 64; i = i + 1) begin
        mem[i] <= 0;
      end
      full <= 0;
      empty <= 1;
      rd_idx <= 0;
      wr_idx <= 0;
    end else begin
      if (wr && !full) begin
        mem[wr_idx] <= din;
        wr_idx <= wr_idx + 2;
        if (wr_idx == 64) begin
          wr_idx <= 0;
        end
        if (!empty) begin
          empty <= 0;
        end
      end else if (rd && !empty && wr_idx != rd_idx) begin
        dout <= mem[rd_idx];
        rd_idx <= rd_idx + 2;
        if (rd_idx == 64) begin
          rd_idx <= 0;
        end
        if (!full) begin
          full <= 1;
        end
      end else begin
        // Do nothing if both wr and rd are 1.
      end
    end
  end

endmodule